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  features  trenchfet  power mosfet  ultra-low r ss(on)  new micro foot  chipscale packaging reduces footprint area, profile (0.65 mm) and on-resistance per footprint area applications  smart batteries for portable devices si8901db vishay siliconix new product document number: 73126 s-41820?rev. a, 11-oct-04 www.vishay.com 1 bi-directional p-channel 20-v (d-s) mosfet product summary v s1s2 (v) r s1s2(on) (  ) i s1s2 (a) 0.060 @ v gs = ? 4.5 v ? 4.4 ? 20 0.080 @ v gs = ? 2.5 v ? 3.9 0.105 @ v gs = ? 1.8 v ? 3.4 1 micro foot device marking: 8901 = p/n code xxx = date/lot traceability code s 2 s 2 bump side view g 2 g 1 4 3 5 6 s 1 s 1 2 backside view 8901 xxx pin 1 identifier ordering information: si8901db-t2?e3 g 2 s 2 g 1 s 1 p-channel absolute maximum ratings (t a = 25  c unless otherwise noted) parameter symbol 5 secs steady state unit source1?source2 voltage v s1s2 ? 20 v gate-source voltage v gs  8 v continuous source1 ? source2 current (t j = 150  c) a t a = 25  c i s1s2 ? 4.4 ? 3.5 c on ti nuous s ource 1 ? s ource 2 c urren t (t j = 150  c) a t a = 85  c i s1s2 ? 3.2 ? 2.5 a pulsed source1?source2 current i sm ? 30 maximum power dissipation a t a = 25  c p d 1.7 1 w maximum power dissipation a t a = 85  c p d 0.8 0.5 w operating junction and storage temperature range t j , t stg ? 55 to 150 package reflow conditions c vpr 215  c package reflow conditions c ir/convection 220 thermal resistance ratings parameter symbol typical maximum unit mi j ti tabit a t  5 sec r 60 75 maximum junction-to-ambient a steady state r thja 95 120  c/w maximum junction-to-foot b steady state r thjf 18 22 c/w notes a. surface mounted on 1? x 1? fr4 board. b. the foot is defined as the top surface of the package. c. refer to ipc/jedec (j-std-020a), no manual or hand soldering.
si8901db vishay siliconix new product www.vishay.com 2 document number: 73126 s-41820?rev. a, 11-oct-04 specifications (t j = 25  c unless otherwise noted) parameter symbol test condition min typ max unit static gate threshold voltage v gs(th) v ss = v gs , i d = ? 350  a ? 0.45 ? 1.0 v gate-body leakage i gss v ss = 0 v, v gs =  8 v  100 na zero gate voltage source current i s1s2 v ss = ? 20 v, v gs = 0 v ? 1  a zero gate voltage source current i s1s2 v ss = ? 20 v, v gs = 0 v, t j = 85  c ? 5  a on-state source current a i s(on) v ss = ? 5 v, v gs = ? 4.5 v ? 5 a v gs = ? 4.5 v, i ss = ? 1 a 0.048 0.060 source1?source2 on-state resistance a r s1s2(on) v gs = ? 2.5 v, i ss = ? 1 a 0.062 0.080  source1 source2 on state resistance r s1s2(on) v gs = ? 1.8 v, i ss = ? 1 a 0.081 0.105  forward transconductance a g fs v ss = ? 10 v, i ss = ? 1 a 7 s dynamic b gate resistance r g 9.5  turn-on delay time t d(on) 13 20 rise time t r v ss = ? 10 v, r l = 10  27 40 ns turn-off delay time t d(off) v ss = ? 10 v , r l = 10  i ss  ? 1 a, v gen = ? 4.5 v, r g = 6  120 180 ns fall time t f 65 100 notes a. pulse test; pulse width  300  s, duty cycle  2%. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
si8901db vishay siliconix new product document number: 73126 s-41820?rev. a, 11-oct-04 www.vishay.com 3 typical characteristics (25  c unless noted) 0 2 4 6 8 10 0.0 0.4 0.8 1.2 1.6 2.0 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0246810 0 2 4 6 8 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.6 0.8 1.0 1.2 1.4 1.6 ? 50 ? 25 0 25 50 75 100 125 150 v gs = 5 thru 2 v 25  c t c = 125  c v gs = 4.5 v i s1s2 = 1 a v gs = 4.5 v v gs = 2.5 v ? 55  c output characteristics transfer characteristics on-resistance vs. drain current v ds ? drain-to-source voltage (v) ? drain current (a) i d v gs ? gate-to-source voltage (v) ? drain current (a) i d ? on-resistance ( r ds(on)  ) i d ? drain current (a) on-resistance vs. junction t emperature t j ? junction temperature (  c) v gs = 1.8 v 1.5 v 0.00 0.04 0.08 0.12 0.16 0.20 012345 i s1s2 = 1 a on-resistance vs. gate-to -source v oltage ? on-resistance ( r ds(on)  ) v gs ? gate-to-source voltage (v) i s1s2 = 5 a ? 0.2 ? 0.1 0.0 0.1 0.2 0.3 0.4 ? 50 ? 25 0 25 50 75 100 125 150 i s1s2 = 350  a threshold v oltage variance (v) v gs(th) t j ? temperature (  c) r ds(on) ? on-resiistance (normalized)
si8901db vishay siliconix new product www.vishay.com 4 document number: 73126 s-41820?rev. a, 11-oct-04 typical characteristics (25  c unless noted) 0 5 30 power (w) single pulse power, junction-to-ambient time (sec) 20 25 10 ? 3 10 ? 2 1 10 600 10 ? 1 10 ? 4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 normalized thermal transient impedance, junction-to-ambient square wave pulse duration (sec) normalized effective transient thermal impedance 1. duty cycle, d = 2. per unit base = r thja = 95  c/w 3. t jm ? t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm 1 1000 10 0.1 0.01 15 10 ? 3 10 ? 2 1 10 ? 1 10 ? 4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 normalized thermal transient impedance, junction-to-foot square wave pulse duration (sec) normalized effective transient thermal impedance 100 10 100 0.1 0.1 1 10 100 *limited by r ds(on) 0.001 1 t c = 25  c single pulse 1 s 10 s dc, 100 s ? drain current (a) i d safe operating area 10 0.01 100 ms 10 ms 1 ms 10  s, 100  s v ds ? drain-to-source voltage (v) *v gs  minimum v gs at which r ds(on) is specified
si8901db vishay siliconix new product document number: 73126 s-41820?rev. a, 11-oct-04 www.vishay.com 5 package outline micro foot: 6-bump (2 x 3, 0.8-mm pitch) recommended land mark on backside of die e e 6  0.30  0.31 note 3 solder mask ? 0.4 8901 xxx d e s e e s bump note 1 a a 2 a 1 notes (unless otherwise specified): 1. 6 solder bumps are eutetic 63sn/37pb with diameter 0.37 ? 0.41 mm 2. backside surface is coated with a ag/ni/ti layer 3. non-solder mask defined copper landing pad. 4. laser marks on the silicon die back e note 2 b diameter e millimeters* inches dim min max min max a 0.600 0.650 0.0236 0.0256 a 1 0.260 0.290 0.102 0.114 a 2 0.340 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 d 1.52 1.6 0.0598 0.0630 e 2.32 2.4 0.0913 0.0945 e 0.750 0.850 0.0295 0.0335 s 0.380 0.400 0.0150 0.0157 * use millimeters as the primary measurement. vishay siliconix maintains worldw ide manufacturing c apability. pr oducts may be manufactured at on e of several qualified locati ons. reliability data for silicon technology and package reliability repr esent a composite of all qualified locations. for re lated documents such as package/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?73126 .
legal disclaimer notice vishay document number: 91000 www.vishay.com revision: 08-apr-05 1 notice specifications of the products displayed herein are subjec t to change without notice. vishay intertechnology, inc., or anyone on its behalf, assume s no responsibility or liability fo r any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale.


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